DIGITAL LOGIC - TRI-STATE GATE
Tri-state gates are designed so that the output exhibits three distinct states. It may act as a normal gate with a low-impedance logic 1 and logic 0 when the control input is enabled. A third state, having very high output impedance occurs when the control input is disabled.
Tri-state gates are designed so that the output exhibits three distinct states. It may act as a normal gate with a low-impedance logic 1 and logic 0 when the control input is enabled. A third state, having very high output impedance occurs when the control input is disabled.
Function
The function of a tri-state
gate is similar to a switch with one input tied to high impedance, the other to
the output of an inverter.
Truth Table
The various combinations of
data and control and the resulting outputs are shown in the truth table.
Example
In the exam le below, tri-state
control is used to allow more than one device to snare a common bus, but not at
the same time.
Timing Diagram
The timing diagram shows that
when the control is disabled (0) the output is at a null (high impedance);
when the control is enabled (1) the input data is inverted and appears at the
output.
FIGURE :TRI-STATE
GATES
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