Self-test of the AFS and peripherical systems

• Self-test of the AFS and peripherical systems:

- Most of the systems or units have their own built-in self-test,

- For the AFS they consist in power-up and AFS tests,

- The purpose of the self-tests is to check the integrity of the hardware within each computer and the integrity of most of the LRUs without BITE but in direct connection with the computer (sensors, actuators, switches...),

- These tests do not rely on the control laws and logics of the avionics program but are solely turned towards the components integrity.

For the AFS when power up and AFS test are successful it is considered that all AFS safety devices are operative and that nearly all components within the AFS are healthy.

1.3 IN FLIGHT HELP

Performance and Failure Assessment Monitor (PAFAM) System uses a digital computer and a colour CRT display, its purpose being to operate in conjunction with an automatic flight guidance system (AFGS) to provide a flight crew with a prediction of the quality of an automatic approach and landing manoeuvre being carried out in low visibility. It monitors aircraft attitude, heading, and performance of the AFGS and makes a continual assessment of whether or not a successful automatic landing will result. In the event that the progress of the manoeuvre is unsuccessful, a `TAKEOVER' command is displayed; if the aircraft is being flown manually with commands from the flight director system, and the approach path is unacceptable, the legend NO TRACK is displayed.

The computer accepts electrical input signals from those sensors and sub-systems necessary for proper operation of the AFGS and auto throttle/speed control system. Electrical power is applied when the AFGS LAND ARM mode or flight director ILS modes of operation are selected, and the system is automatically switched to its operational condition when the ILS localizer and glide slope are being tracked.

The signal inputs to the computer are a.c. and d.c. analog and are multiplexed into an A/D converter which is under programmed memory control by one of two control processors in the computer; this processor performs most of the landing performance and prediction computations. Discrete signal inputs are multiplexed directly into the second processor, which provides display drive commands, landing system failure assessment, and controls signals for discrete outputs. Interconnection between the two processors is through two 18-bit storage registers.

Analog signals from the computer are applied to the display electronics unit, and they provide commands for blanking out a portion of two raster-scanned CRT display units (one for each pilot) as well as commands which determine the location of desired characters in the display.